1. Field of the Invention
The present invention relates to a semiconductor storage device including a counter noise generator and a method of controlling the same.
2. Description of Related Art
A DRAM (Dynamic Random Access Memory) includes complementary bit lines arranged in perpendicular to word lines, and memory cells arranged in intersections of the word lines and the complementary bit lines in matrix form.
FIG. 9 shows one example of a schematic configuration diagram of a related DRAM 900. The DRAM 900 includes memory cell areas (911, 912, . . . , 91m) where a plurality of memory cells are arranged, sense amplifier areas (921, 922, . . . , 92m), an HVDD power source 930 (output voltage VDD/2), and a buffer circuit 940. Data written into the memory cells are transferred to the memory areas (911, 912, . . . , 91m) from the buffer circuit 940 through each of the sense amplifier areas (921, 922, . . . , 92m) by common data lines DBus.
FIG. 10 shows one example of a circuit configuration diagram of the memory cell area 911 and the sense amplifier area 921. As shown in FIG. 10, the memory cell area 911 includes memory cells 1011, 1012, . . . , 101n connected to a bit line BT or BN. In this specification, a complementary bit line pair BT and BN of True and Bar will be referred to as BT/BN. The sense amplifier area 921 includes an equalizer 1021, a sense amplifier 1022, and a column selector 1023. The equalizer 1021 sets a voltage of the complementary bit line pair BT/BN to VDD/2, the sense amplifier 1022 amplifies a potential difference of the complementary bit line pair BT/BN, and the column selector 1023 connects the complementary bit line pair BT/BN and the common data lines DBus (True/Bar).
Each memory cell includes a gate transistor and a capacitor. For example, in the memory cell 1011, a gate transistor Tr1 includes a gate connected to a word line WL1, one of a drain and a source connected to a bit line BT1, and the other of the drain and the source connected to one terminal of a capacitor C1 through a cell node SN1. The other terminal of the capacitor C1 is connected to the HVDD power source 930. Other memory cells also have the same configurations as described above.
Now, we consider a case in which data “H” held in the memory cell 1011 is rewritten to “L” as an example. First, a word select signal of the word line WL1 is raised to turn on the gate transistor Tr1. Accordingly, the cell node SN1 and the bit line BT are connected through the gate transistor Tr1. Next, the potential difference of the complementary bit line pair BT/BN is amplified by the sense amplifier 1022. Then the column selector 1023 is turned on by a column select signal Y, and the L level (ground potential GND) for writing is transferred to the bit line BT from the buffer circuit 940 through the common data line DBus (True).
Since there is a difference in an ability of the amplifier between the buffer circuit 940 and the sense amplifier 1022, the potential of the bit line BT inverts from the H level to the L level. Therefore, the potential of the cell node SN1 is in the L level (ground potential GND), and the capacitor C1 releases charge into a bit line side. In summary, the charge flows in a counter plate of the capacitor C1 so that the current is supplied to the capacitor C1 from the HVDD power source 930. Then the word select signal of the word line WL1 is fallen to turn off the gate transistor Tr1. The cell node SN1 and the bit line BT are disconnected to complete the data writing into the memory cell 1011. At this time, the data held in the memory cell 1011 is “L”. When the data “L” held in the memory cell 1011 is rewritten to “H”, the potential of the above operation will be reversed.
As stated above, the voltage of the cell node of each memory cell fluctuates when the data held in the memory cell is rewritten. Then the current flows into the HVDD power source 930 which is capacity-coupled with the cell node by the capacitor or the current is supplied from the HVDD power source 930. Thus a noise current against the HVDD power source 930 is produced.
On the other hand, in recent years, a semiconductor device in which a logic part such as a controller and a DRAM part (hereinafter referred to as eDRAM: embedded DRAM) are mounted in one chip has become popular such as a system LSI (Large Scale Integration). Since the eDRAM and the logic part are mixedly mounted on the chip as stated above, there is little limitation on the interface between the controller and the eDRAM, and power saving operation can be realized. Therefore, there is a tendency of increasing the number of I/Os between the controller and the eDRAM for the purpose of performing high speed data transmission. In some cases, the number of I/Os accessing at one time is equal to or more than 256 bits. When the number of I/Os is 256 bits, for example, it is expressed as “×256 bits”, which means that there are 256 (512 in both True and Bar) common data lines DBus (True/Bar).
However, it is difficult to make the DRAM part (eDRAM) larger because total chip area of the system LSI is limited. Accordingly, the size of the eDRAM cannot be made larger despite the fact that the number of I/Os accessing at one time between the controller and the DRAM has been on the increase as described above. In other words, the ratio of the number of memory cells in which the data is rewritten to the number of memory cells in which the data is not rewritten increases in accessing the memory.
As shown in FIGS. 9 and 10, the HVDD power source 930 is connected to the capacitors of all the memory cells of the DRAM 900. When the number of I/Os accessing the memory cells at one time is small, a parasitic capacity between the capacitor of the memory cell in which the data is not rewritten and the HVDD power source 930 is sufficiently large with respect to the noise current; therefore there is no problem raised even when the ability of the HVDD power source 930 is not so high. However, in a case where the voltage fluctuation due to the rewriting of the data from the H level to the L level is caused in the cell node as described above when the ratio of the number of memory cells in which the data is rewritten to the number of memory cells in which the data is not rewritten is large, as an example, the influence of the noise current generated by the voltage fluctuation on the HVDD power source 930 cannot be ignored. Since the noise current fluctuates the output voltage of the HVDD power source 930, the cell nodes in the counter plates of all the capacitors connected to the HVDD power source 930 are influenced. This may cause degradation of quality of the data held in the capacitor of the memory cell.
Furthermore, since the manufacturing process has been miniaturized in recent years, the power supply voltage VDD, and the reference voltage HVDD which is VDD/2 have also been decreasing. Therefore, the noise described above influences more on the HVDD power source outputting the reference voltage which has been decreasing.
In order to overcome this problem, it would be effective to increase response speed or a number of stabilizing capacitors for removing ripple of the HVDD power source. However, an area of a decoupling capacitor needs to be increased in order to increase the number of stabilizing capacitors. Furthermore, the response of the voltage determination circuit in the HVDD power source needs to be enhanced in order to increase the response speed, which increases the power consumption of the amplifier of the voltage determination circuit. Accordingly, the power consumption of the semiconductor storage device or the area required in the semiconductor storage device increases, which causes an adverse effect.
Japanese Unexamined Patent Application Publication No. 2002-184173 discloses a technique capable of reducing coupling noise on a cell plate voltage line. In this technique, a memory array includes a main cell and a dummy cell, and inversion data of the data written into the main cell is written into the dummy cell. However, according to this technique, the noise can further be produced before writing depending on the data.
As stated above, according to the semiconductor storage device in the related art, the noise current is generated in the reference voltage power source which is capacity-coupled to the counter plate of the capacitor of the cell node due to the voltage fluctuation of the cell node generated when the data held in the memory cell is rewritten, which makes the output voltage of the reference voltage power source unstable.